The speed of data processing of an arithmetic processing device such as a central processing unit (CPU) is increased by providing the arithmetic processing device with a cache memory that retains a part of information stored by a main storage device. A cache memory storing instructions executed by the arithmetic processing device is referred to also as an instruction cache. A cache memory storing data processed by the arithmetic processing device is referred to also as a data cache.
A method has been proposed which uses one of a plurality of ways and makes the way operate as a direct-mapped type in an instruction cache of a set-associative type including the ways, and which thereby reduces power consumption as compared with a case where the plurality of ways are operated. In addition, a method has been proposed which stops the operation of a way determined in advance on the basis of the execution of a dedicated instruction in an instruction cache of a set-associative type, and which thereby reduces power consumption as compared with a case where all of ways are operated. Incidentally, the instructions retained in the instruction cache are not rewritten, so that coherency (consistency) between the instructions retained by the instruction cache and the instructions retained by the main storage device is maintained.
Further, a method has been proposed which switches a given number of a plurality of ways to an on-chip memory use on the basis of an instruction by a program, and thereby makes effective use of the cache memory according to the characteristic of the program. Data retained by the ways to be used as an on-chip memory is written back to a main storage device before the ways are switched to the on-chip memory.
As examples of the related art, Japanese Laid-open Patent Publication No. 2003-131945, Japanese Laid-open Patent Publication No. 2000-298618, and Japanese Laid-open Patent Publication No. 2008-310465 are known.
When data is rewritten in a cache memory, coherency between data retained by the cache memory and data retained by a main storage device is not maintained. In a cache memory of a set-associative type, when the operation of a given number of a plurality of ways is stopped to reduce power consumption, data retained in the ways to be stopped from operating is deleted. A part of the deleted data which part has been rewritten in the cache memory is written back to the main storage device to maintain the coherency. However, when a memory access request for deleted data occurs before the data rewritten in the cache memory is written back to the main storage device, old data before the writing back may be transferred from the main storage device to the cache memory.